1. Field of the Invention
The present invention relates generally to signal processing circuits, and more specifically to a switch-capacitor circuit for reducing the Inter-Symbol-Interference (ISI) effect.
2. Background Art
Switch-Capacitor (SC) circuits are widely used in all kinds of signal processing circuits and are based on capacitors that are switched to signal voltages. Typically, the switching takes place at the beginning of every clock cycle. After the switching, the capacitor is charged to the signal voltage. This process takes some time and the speed of charging depends on the time constant involved.
At the same time the capacitor is being charged up to its new voltage, it is being discharged from the voltage it had at the end of the previous clock cycle.
Both the charging and discharging process can be described by the same time constant and therefore can have the same speed. Because the discharging is imperfect, some voltage from the previous clock cycle may remain. This phenomenon is called Inter-Symbol-Interference (ISI).
For most circuits, the accuracy that is required for the charging process is usually similar to the accuracy required for the discharging process. In such a case, ISI does not significantly limit the maximum clock frequency. However, there exist certain types of circuits which do not require a high level of accuracy for charging, but still require a high level of accuracy for discharging. In such cases, ISI does limit the maximum clock frequency. Thus, if the ISI problem could be reduced in these types of circuits, the maximum clock frequency of such circuits could be increased. For example, a SubRange ADC consisting of a Coarse and Fine ADC is a circuit affected by ISI. Here, ISI leads to errors in the decision of both the Coarse and Fine decision.
Referring now to FIG. 1, there is shown a simple prior art switch-capacitor circuit 100 having a voltage source 102 having a variable voltage output Vin, an output resistance 104, a capacitor 106, and switches, 108a, 108b, and 108c, that are operated during non-overlapping clock phases phi(1) (switches 108a, 108b) and phi(2) (switch 108c). Vin may be the output voltage of a circuit, such as a Track-Hold (TH) amplifier (not shown).
As can be seen from FIG. 1, the voltage source 102 is coupled to the switch 108a via a line 102a. The switch 108a is coupled to the capacitor 106 via a line 106a, and to the switch 108c via a line 106b. Further, the capacitor 106 is coupled to the switch 108b via a line 106c. As is further shown in FIG. 1, the voltage source 102 is coupled to the switch 108c via a line 102b, and a line 102c, and to the switch 108b via the line 102b, and a line 102d. 
During clock phase phi(1), the capacitor 106 is charged to Vin through resistance 104. During the same time interval, capacitor 106 is also being discharged through resistance 104. The effect of discharging of the previous voltage across the capacitor 106 is clearly visible in the nodal voltage Va. At the beginning of phi(1), Va starts at the previous value of Vin. Because Va is not equal to Vin at the end of phi(1), Vb during phi(2) is also not equal to Vin during phi(1). Thus, both voltages Va and Vb are not ideal.
Some circuits are negatively impacted by the non-ideal behavior of Va and others more by the non-ideal behavior of Vb. For example, a SubRange ADC with a Coarse and Fine ADC is negatively affected by the non-ideal behavior of Va. The ISI kick comes from the Fine ADC (modeled by the capacitor C). The Coarse ADC is also connected to node a during phi(1). The amplifiers inside the Coarse ADC amplify Va. The outputs of these amplifiers are highly distorted because of the ISI kick and this has a negative impact on the Coarse-Fine timing of the SubRange ADC. An example of a circuit that is sensitive to the non-ideal behavior of Vb is the Fine ADC of a SubRange ADC. When Vb differs too much from Vin, distortion inside the ADC occurs. Thus, what is needed is an improved switch-capacitor circuit that improves the non-ideal behavior of Va and Vb.
One method for reducing the ISI effect is to increase the bandwidth of the circuits. However, because this solution also increases current consumption, it is neither an attractive nor practical solution.
Another method for reducing ISI is based on shorting the capacitor 106 for a short amount of time. Referring now to FIG. 2, there is shown a switch-capacitor circuit in which ISI cancellation is achieved by shorting the capacitor (here: a capacitor 206). Corresponding to the switch-capacitor circuit 100 shown in FIG. 1, the switch-capacitor circuit 200 shown in FIG. 2 comprises a voltage source 202 having a variable voltage output Vin, an output resistance 204, a capacitor 206, and switches, 208a, 208b, and 208c, that are operated during non-overlapping clock phases phi(1) (switches 208a, 208b) and phi(2) (switch 208c). Further, the switch-capacitor circuit 200 comprises a switch 208d for shorting the capacitor 206.
As can be seen from FIG. 2, the voltage source 202 is coupled to the switch 208a via a line 202a. The switch 208a is coupled to the capacitor 206 via a line 206a, and to the switch 208c via a line 206b. Further, the capacitor 206 is coupled to the switch 208b via a line 206c. As is further shown in FIG. 2, the voltage source 202 is coupled to the switch 208c via a line 202b, and a line 202c, and to the switch 208b via the line 202b, and a line 202d. In addition, the switch 208d is coupled to the capacitor 206 (and to the switches 208a, 208c) via a line 208e, and to the capacitor 206 (and to the switch 208b) via a line 208f. 
The above shorting of the capacitor 206 by the switch 208d is illustrated by switch phi(3) at the beginning of the clock cycle phi(1). Although this solution is relatively simple to implement, this technique has several disadvantages. One disadvantage is that the output terminal of the amplifier is temporarily shorted which creates huge current spikes in the amplifier. Another disadvantage is that the time to charge the capacitor 206 up to Vin (during phi(1)) effectively becomes shorter since no charging is possible during phi(3). The charging of the capacitor 206 begins after phi(3). As a result, the maximum clock frequency of the circuit effectively decreases depending on the duration of phi(3).
Therefore, what is needed is a new technique and circuit that reduces the ISI effect without the problems encountered in the prior art.